1. Field of the Invention
The present invention relates to a semiconductor element structure and a method for forming the semiconductor element structure. More particularly, the present invention relates to a semiconductor element structure with an inter-gate bridge channel and a method for forming the semiconductor element structure.
2. Description of the Prior Art
The gate electrodes in a PMOS and NMOS of a static random access memory (SRAM) based on the complementary metal-oxide semiconductor (CMOS) structure are usually connected to each other. If such devices are manufactured by a high-K/metal gate replacement procedure, however, the poly-Si and the gate dielectric layer in the gates of the PMOS and the NMOS is removed in different steps to be replaced by the corresponding conductive metal gate and gate dielectric layer. Just after the deposition of the high-K materials and the metal gate materials, the electric connection between the metal gates in the PMOS and the NMOS is lost due to the isolation formed by the high-K materials. Therefore, a technical strategy is needed to restore the electric connection between the metal gates in the PMOS and the NMOS.
An electrical connection plan is provided in U.S. Pat. No. 6,849,511. A dishing phenomenon is available on the surface of the material with higher removal rate by taking advantage of different removal rates between different materials by CMP and this area is taken as the space for the electrical connection material for the metal gates in the PMOS 101 and the NMOS 102, as shown in FIG. 1. Because, however, such a dishing space is too thin to be a suitable electrical connection as well as to be easily controlled and to stably and effectively maintain a sufficient electrical connection for the metal gates in the PMOS 101 and the NMOS 102, only an electrical connection with overly high electrical resistance is obtained.
Another electrical connection plan is provided in U.S. Pat. No. 6,653,698. Space for the electrical connection is obtained by entirely back-etching the high-K materials and the metal gates in the PMOS 201 and the NMOS 202, as shown in FIG. 2. Because, however, the back-etching is non-selective in the absence of a photoresist, the uniform thickness is not easily controlled and the height of the semiconductor device is compromised.
Still another electrical connection plan is provided in U.S. Pat. No. 7,045,428. The high-K materials are directly converted into metals to realize the electrical connection between the metal gates.
In spite of the provided technical plans, a stable and reliable method is still needed to construct a sufficient electrical connection of the metal gates in the PMOS and the NMOS.